Power semiconductor modules are known as such and used in a broad application range. Power semiconductor devices may comprise power semiconductor switches which may switch currents of more than 10 A and/or voltages of more than 500V.
The trend in power semiconductor technology goes into the direction of fast-switching devices. Shorter switching times can be obtained by optimizing silicon (Si) based devices as well as using devices based on wide band gap semiconductor materials, e.g., silicon-carbide (SIC) or gallium-nitrite (GaN). However, electromagnetic parasitics in the power module give rise to severe switching distortions in power modules, thereby limiting the maximum achievable switching times.
Regarding the above, power electronics modules for fast switching semiconductors therefore require very low stray inductance.
As a general rule, the stray inductance is determined by the physical area of the commutation cell. In 2D, the current paths have to be placed next to each other. The physical area of the commutation cell is then roughly proportional to the footprint area of the substrate. In practice, the stray inductance of standard planar power modules can therefore not easily be reduced to values below ˜5-10 nH. For fast switching semiconductors with rise-times of ˜10 ns, this value is often not acceptable.
During switching, the current transients in the stray inductance of the commutation cell induces a voltage. During turn-on of the switch, this voltage leads to a slower commutation and higher switching losses. During turn-off of the switch, the voltage adds to the already applied DC link voltage and induces an overvoltage, thereby exerting stress on the switch and requiring de-rating.
This is described in O. Mühlfeld and F. W. Fuchs, “Optimization of the stray inductance in three-phase MOSFET power modules aided by means of PEEC simulation,” in Proceedings of 13th European Conference on Power Electronics and Applications (EPE), 2009. According to this document, a compact DBC based three-phase power module for use in 5 to 20 kW converters for automotive application is described. According to this document, a three dimensional stack of MOSFET chips is provided, which, however, is described not to be assembled with nowadays packaging methods.
The impact of stray inductance on total switching losses is complex, but as a general rule, lower inductance also reduces switching losses. Regarding this, W. Rusche and M. Bäassler, “Influence of stray inductance on high-efficiency IGBT based inverter designs,” Power Electronics Europe, vol. 7, 2010, generally describes the influence of stray inductance on high efficiency IGBT based inverter designs.
The stray inductance of the commutation cell forms a resonant circuit with the output capacitance of the open semiconductor switch. During switching, this resonant circuit is excited and emits disturbances at a frequency f=½π√LC, which is typically in the EMI regime. The problem will become even worse for devices from wide band gap semiconductor materials (SiC, GaN) with typically higher output capacitance, see J. Biela, M. Schweizer, S. Waffler and J. W. Kolar, “SiC versus Si—Evaluation of Potentials for Performance Improvement of Inverter and DC-DC Converter Systems by SiC Power Semiconductors,” IEEE Transactions on Industrial Electronics, vol. 58, no. 7, pp. 2872-2882, 2011.
C. Martin, J. M. Guichon, M. Schanen and R. J. Pasterczyk, “Gate Circuit Layout Optimization of Power Module Regarding Transient Current Imbalance,” IEEE Transactions on Power Electronics, vol. 21, pp. 1176-1184, 2006 describes that during switching, the inductive coupling between the stray inductance of the commutation cell and the inductance of the gate circuit disturbs the gate signal. This effect is most significant for several paralleled switches, when slightly different coupling coefficients can produce a dramatic current imbalance during switching.
C. M. Johnson, A. Castellazzi, R. Skuriat, P. Evans, J. Li and P. Agyakwa, “Integrated High Power Modules,” in Proceedings of 7th International Conference on Integrated Power Systems (CIPS), 2012, mainly relates to improving thermal management for power semiconductor modules. It is further described that stray inductance of half bridge-modules may be reduced by providing an improved layout, such as by using planar or sandwich packages.
In S. Li, L. M. Tolbert, F. Wang and Z. P. Fang, “Reduction of stray inductance in power electronic modules using basic switching cells,” in Proceedings of 2010 IEEE Energy Conversion Congress and Exposition (ECCE), 2010, a packaging for power electronics is described which shall reduce stray inductance.
In P. Beckedahl, M. Spang and O. Tamm, “Breakthrough into the third dimension? Sintered multi-layer flex for ultra-low inductance power modules,” in Proceedings of 8th International Conference on Integrated Power Systems (CIPS), it is describes that commutation inductances of a half bridge power module may be reduced if the wire-bonds for topside contacts are replaced by planar bonds using flexible sheets.
WO 2014/021077 A1 describes a multilayer substrate and a power module using a multilayer substrate. According to this document, the multilayer substrate particularly serves for providing a metal wiring having low resistance to conduction.
WO 2014/0117524 A1 describes a power semiconductor module which is described to be capable of being manufactured without performing separate wire bonding. Such a power semiconductor device comprises a multilayer substrate formed by stacking a plurality of substrates and electrically connecting the power semiconductor devices and a lead frame.
US 2012/0267149 A1 describes a method of manufacturing a power module and a power module substrate used in a semiconductor apparatus that controls a large electric current and a large voltage. According to this document, multilayers of ceramic substrates and metal plates are laminated, wherein the metal plates on both sides can be in a connected state. This document, however, does not focus on the specific arrangement of different power semiconductor devices.
US 2009/0039498 A1 relates to power semiconductor modules. Such power semiconductor modules comprise one or more power semiconductor chips which are arranged on a plane ceramic substrate which includes a metallization on at least one side. With regard to the substrate, the latter may be designed as a multilayer substrate which comprises a group of metal layers and a group of ceramic layers.
EP 0 688 053 A1 describes power semiconductor modules especially in a half bridge configuration. Conventional switches and diodes may be supported by substrates as it is generally known in the art. The corresponding substrates can be arranged on two sides of a cooler.
In conventional semiconductor power electronics half-bridge modules, a significant part of the commutation loop is formed in the plane of a ceramic substrate. Such a conventional module package may provide good performance for chips based on silicon as semiconductor, wide bandgap- (WBG-) semiconductors require considerably improved switching performance of the module.
However, there have already been presented several promising packaging concepts. These concepts are trying to optimize electromagnetic interference (EMI) and electromagnetic compatibility (EMC) by low strain inductance (La) module design focusing on optimization of the loop size including power terminals loop contribution. A typical approach is a compact-flat package.
Especially regarding power semiconductor modules having low stray inductance, there is, however, still potential for improvements.
US 2014/0152373 A1 discloses a power semiconductor module, comprising two power semiconductor devices, whereby the power semiconductor devices comprise power semiconductor transistor and a power semiconductor diode. A first substrate is provided for carrying the power semiconductor transistor in a first plane and the first plane lying parallel to the plane of the first substrate. The power semiconductor diode is provided in a second plane and the first plane is positioned between the first substrate and the second plane in a direction normal to the first plane.